1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device including a fuse set provided for writing relief address information therein. The present invention also relates to a relief-address-information writing device and relief-address-information writing method for writing relief address information into the semiconductor device.
2. Description of Related Art
A semiconductor device represented by a DRAM (Dynamic Random Access Memory) often includes an address relief circuit that replaces an inoperative and failed memory cell with a redundancy memory cell to relieve the address of the failed memory cell. The address of the failed memory cell, that is, relief address information is detected in an operating test performed at the time of production, and detected relief address information is written into the semiconductor device in question while it is in a wafer state.
As a method of writing relief address information into a semiconductor device, a method has been widely used, which includes cutting a fuse element by irradiating laser beams. However, this method requires devices such as a laser trimmer and it cannot write relief address information into a plurality of semiconductor devices on a wafer at the same time, and therefore the method has a problem of taking a long time for writing.
Meanwhile, a method of storing relief address information using an element called anti-fuse element has commanded attention in recent years (Japanese Patent Application Laid-open No. 2004-303354 or United States Patent Application Publication number 2004/0213056). Initially, the anti-fuse element is in an insulation state, and as a high voltage is applied to cause breakdown, it makes a transition to a conduction state. The anti-fuse element once changed to the conduction state cannot return to the insulation state. Therefore, it can achieve nonvolatile and irreversible retention of information, like usual fuse elements. In this manner, writing into the anti-fuse element is performed electrically, and thus it is possible to write relief address information into a plurality of semiconductor devices on a wafer in parallel.
FIG. 8 is a flowchart for explaining a method of writing relief address information into a plurality of semiconductor devices on a wafer in parallel.
First, a test command is issued to write-target semiconductor devices in common to cause these semiconductor devices to make an entry into a test mode (step S1). Next, after resetting an address counter in a relief-address-information writing device (a tester) (step S2), a determination is made on each of the semiconductor devices whether address information in question corresponds to relief address information (step S3). As a result, to the semiconductor device corresponding to the relief address information (step S3: YES), an enable signal is supplied to instruct writing the relief address information (step S4). On the other hand, to the semiconductor device that does not correspond to the relief address information (step S3: NO), no enable signal is supplied, and as a result, the relief address information is not written. Thus, the relief address information can be written selectively into plural semiconductor devices.
The above operation is performed repeatedly by incrementing the value in the address counter (steps S3 to S6). Such an operation is performed until the value in the address counter indicates a maximum value and finally a series of write processing is completed when the value in the address counter indicates the maximum value (step S5: YES).
The method shown in FIG. 8, however, requires performing the processing mentioned above over the entire address space. Therefore, there is a problem that it takes a relatively long time until a series of write processing is completed. To explain this problem with specific numbers, when the address space contains 8k (=8192) addresses and the time required for processing one address is 70 ms, it takes about 10 minutes to complete a series of write processing.